1. Field
The present disclosure relates generally to apparatus and methods for dynamic data-based scaling of data, and more specifically to apparatus and methods for dynamic scaling of data stored in a memory based on the data itself, such as in a Fast Fourier Transform (FFT) computation or other iterative processing computations of known scaling to minimize the bit-width of the data path.
2. Background
Fourier transform computation is a part of all Orthogonal Frequency Division Multiplexed (OFDM) based communication systems. In particular, the Fourier transform of an input sequence is typically computed by employing Fast Fourier Transform (FFT) algorithms. This FFT operation can be computationally expensive in a wireless device in terms of both power consumption and area in a computation circuit such as an ASIC. The design of the data path for FFT computation is often complicated and needs to accommodate a very high dynamic range (e.g., as high as 35-45 dB), which is a result of channel variation, in-band and out-of-band jammers, etc. A solution for accommodating this high dynamic range could include a static scaling scheme such as a Digital controlled Variable Gain Amplifier (DVGA) multiplication of the input sequence before the FFT computation. Such a scheme would need to take into consideration variable network loading and unknown frequency domain power distributions, for example. However, additional headroom would have to be allocated in the bit-widths to account for this dynamic range, thus tending away from minimization of the computation bit width of the FFT.
It is further noted that FFT algorithms typically transform an input sequence by decomposing the input sequence (typically a power of 2) into smaller Fourier transforms that are a power of two (2). Successive computation of these smaller Fourier transforms (also called butterflies) engenders a larger FFT. Additional headroom would also need to be provided for this dynamic range. Thus, optimization of the FFT computation block is an important design consideration. Accordingly, a need exists for minimizing the computation bit-width of a data path for an iterative process of known scaling output, such as a staged FFT algorithm, while still providing adequate bit-width to ensure adequate performance.